view docs/manual/x800.html @ 418:3832a68d83ef

Fix internal compiler error on "var2 = var1 + 1" patterns This appears to be the correct fix. It was provided by Tormod Volden (debian.tormod@gmail.com). The final commit is substantially different from Tormod's submission mostly due to housecleaning (removing the old patches and updating the README). Tormod's comments follow. The original addhi_mem_1 "insn" instruction pattern /matches/ two memory operands, just with the /constraint/ that these are the same location. A pattern match tells the compiler "you should be able to use this, but you might have to work on it to meet the constraints". For typical constraints on registers the compiler can add "reloads", moving stuff between registers or from memory, until the constraints are met and the instruction can be used. However, in this case, no amount of reloads can make two memory locations the same if they already weren't, so the compiler breaks down and cries "unable to generate reloads". It seems this issue only appears if optimization is enabled. The proof is in gcc's reload.c and is left as an exercise to the reader. Limiting the matching pattern to identical memory operands avoids these situations, while allowing the common "var++" cases. References: The pattern/constraints difference is explained in https://gcc.gnu.org/onlinedocs/gccint/Simple-Constraints.html#index-other-register-constraints-3335
author William Astle <lost@l-w.ca>
date Tue, 29 Mar 2016 21:21:49 -0600
parents fc166b3bbae3
children cad5937314cb
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>3.12. Cycle Counts</A
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>&#13;The following options for displaying cycle counts in listings are provided.
These options are enabled from pragmas on the command line or in the
assembly files themselves.  For compatibility with other assemblers you can
use the "OPT" keyword in addition to "PRAGMA."</P
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>opt c  - enable cycle counts: [8]
opt cd - enable detailed cycle counts breaking down addressing modes: [5+3]
opt ct - show a running subtotal of cycles
opt cc - clear the running subtotal</PRE
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>&#13;The assembler supports both 6809 as well as native-mode 6309 cycle counts.
In 6309 mode the counts are displayed in parenthesis instead of brackets. 
In addition, some operations have a variable cycle count.  In this case a
"+?" is displayed to alert the reader.  Sample output is shown below.</P
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>266f 7d25e2     (window.asm):00313 [7]     7       move   tst   putflg
2672 2602       (window.asm):00314 [5]     12             bne   a@
2674 1e13       (window.asm):00315 [8]     20             exg   x,u
2676 0dd6       (window.asm):00316 [6]     26      a@     tst   is6309
2678 2618       (window.asm):00317 [5]     31             bne   exit@
                (window.asm):00318                        opt   6309
267a 10860085   (window.asm):00319 (4)     35      b@     ldw   #133
267e 113813     (window.asm):00320 (6+?)   41             tfm   x+,u+
2681 30881b     (window.asm):00321 (4+1)   46             leax  27,x
2684 33c81b     (window.asm):00322 (4+1)   51             leau  27,u
2687 4a         (window.asm):00323 (1)     52             deca
2688 26f0       (window.asm):00324 (5)     57             bne   b@</PRE
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