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Fix internal compiler error on "var2 = var1 + 1" patterns
This appears to be the correct fix. It was provided by Tormod Volden
(debian.tormod@gmail.com). The final commit is substantially different from
Tormod's submission mostly due to housecleaning (removing the old patches
and updating the README). Tormod's comments follow.
The original addhi_mem_1 "insn" instruction pattern /matches/ two
memory operands, just with the /constraint/ that these are the same
location. A pattern match tells the compiler "you should be able to use
this, but you might have to work on it to meet the constraints". For
typical constraints on registers the compiler can add "reloads", moving
stuff between registers or from memory, until the constraints are met
and the instruction can be used. However, in this case, no amount of
reloads can make two memory locations the same if they already weren't,
so the compiler breaks down and cries "unable to generate reloads".
It seems this issue only appears if optimization is enabled. The proof
is in gcc's reload.c and is left as an exercise to the reader.
Limiting the matching pattern to identical memory operands avoids
these situations, while allowing the common "var++" cases.
References:
The pattern/constraints difference is explained in
https://gcc.gnu.org/onlinedocs/gccint/Simple-Constraints.html#index-other-register-constraints-3335
| author | William Astle <lost@l-w.ca> |
|---|---|
| date | Tue, 29 Mar 2016 21:21:49 -0600 |
| parents | 2c24602be78f |
| children |
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LWASM 2.0 ========= LWASM is a cross-assembler for the MC6809 and HD6309 CPUs. It should assemble most reasonable EDTASM compatible source code. This document is not intended to teach assembly language for these CPUs but rather to document the behaviour of LWASM. TARGETS ------- LWASM supports several targets for assembly. These are decb, raw, and obj. The raw target generates a raw binary output. This is useful for building ROMs and other items that are not intended to be loaded by any kind of loader. In this mode, the ORG directive is merely advisory and does not affect the output except for the addresses symbols are defined to have. The decb target generates output that can be loaded with the CLOADM or LOADM commands in Color Basic. There will be approximately one segment in the output file for every ORG statement after which any code is emitted. (That is, two ORG statements in a row will not generate two output segments.) This is approximately equivalent to running A/AO in EDTASM. The obj target generates output that is intended to be linked later with LWLINK. This target disallows the use of ORG for defining anything other than constants. In this target, source files consist of a number of sections (SECTION/ENDSECTION). Nothing outside of a section is permitted to cause any output at all. Use of an ORG statement within a section is an error. This target also permits tagging symbols for export (EXPORT) and marking a symbol as externally defined (IMPORT/EXTERN). The linker will resolve any external references at link time. Additionally, any inter-section references will be resolved by the linker. All code in each section is assembled with an implicit origin of 0. SETDP has no effect because the assembler has no idea what address the linker will assign to the code when it is linked. Any direct addressing modes will default to extended to allow for the linker to perform relocations. Intersegment references and external references will use 16 bit relative addressing but intrasegment internal references may use 8 bit relative addressing. Forced 8 bit direct modes are probably an error but are permitted on the theory that the programmer might know something the assembler doesn't.