# HG changeset patch
# User lost
# Date 1244765943 0
# Node ID 560843a951f74a98148809f04a17d3b6b7cbf2b4
# Parent  4c60c3a09597be57cde780593015e2bc9012dc31
Added compatibility alternatives to TFM

diff -r 4c60c3a09597 -r 560843a951f7 ChangeLog
--- a/ChangeLog	Fri Jun 12 00:06:24 2009 +0000
+++ b/ChangeLog	Fri Jun 12 00:19:03 2009 +0000
@@ -18,6 +18,9 @@
 [+] Added includebin directive to include the literal contents of a binary
     file at the current assembly address. [LWASM]
 [+] Added || and && as boolean or and boolean and respectively [LWASM]
+[+] Added COPY, COPY-, IMP, EXP, TFRP, TFRM, TFRS, TFRR as alternatives to
+    the TFM instruction variations for compatibility with other assemblers
+    [LWASM]
 
 Version 2.4
 
diff -r 4c60c3a09597 -r 560843a951f7 lwasm/insn_tfm.c
--- a/lwasm/insn_tfm.c	Fri Jun 12 00:06:24 2009 +0000
+++ b/lwasm/insn_tfm.c	Fri Jun 12 00:19:03 2009 +0000
@@ -109,3 +109,31 @@
 	}
 	lwasm_emit(as, l, (r0 << 4) | r1);
 }
+
+OPFUNC(insn_tfmrtor)
+{
+	int r0, r1;
+	static const char *regs = "D X Y U S       A B     0 0 E F ";
+	
+	lwasm_emitop(as, l, instab[opnum].ops[0]);
+	// register to register (r0,r1)
+	// registers are in order:
+	// D,X,Y,U,S,PC,W,V
+	// A,B,CC,DP,0,0,E,F
+	r0 = lwasm_lookupreg2(regs, p);
+	if (r0 < 0 || *(*p)++ != ',')
+	{
+		register_error(as, l, 1, "Bad operand");
+		r0 = r1 = 0;
+	}
+	else
+	{
+		r1 = lwasm_lookupreg2(regs, p);
+		if (r1 < 0)
+		{
+			register_error(as, l, 1, "Bad operand");
+			r0 = r1 = 0;
+		}
+	}
+	lwasm_emit(as, l, (r0 << 4) | r1);
+}
diff -r 4c60c3a09597 -r 560843a951f7 lwasm/instab.c
--- a/lwasm/instab.c	Fri Jun 12 00:06:24 2009 +0000
+++ b/lwasm/instab.c	Fri Jun 12 00:19:03 2009 +0000
@@ -39,6 +39,7 @@
 extern OPFUNC(insn_bitbit);
 extern OPFUNC(insn_logicmem);
 extern OPFUNC(insn_tfm);
+extern OPFUNC(insn_tfmrtor);
 extern OPFUNC(insn_indexed);
 
 extern OPFUNC(pseudo_org);
@@ -314,6 +315,19 @@
 	// note: 		r+,r+	r-,r-	r+,r	r,r+
 	{ "tfm",	{	0x1138,	0x1139,	0x113a,	0x113b	},	insn_tfm },
 
+	// compatibility opcodes for tfm in other assemblers
+	{ "copy",	{	0x1138, -1, -1, -1},	insn_tfmrtor },
+	{ "tfrp",	{	0x1138, -1, -1, -1},	insn_tfmrtor },
+	
+	{ "copy-",	{	0x1139, -1, -1, -1},	insn_tfmrtor },
+	{ "tfrm",	{	0x1139, -1, -1, -1},	insn_tfmrtor },
+	
+	{ "imp",	{	0x113a, -1, -1, -1},	insn_tfmrtor },
+	{ "tfrs",	{	0x113a, -1, -1, -1},	insn_tfmrtor },
+	
+	{ "exp",	{	0x113b, -1, -1, -1},	insn_tfmrtor },
+	{ "tfrr",	{	0x113b, -1, -1, -1},	insn_tfmrtor },
+
 	{ "tfr",	{	0x1f,	-0x1,	-0x1,	-0x1	},	insn_rtor },
 	{ "tim",	{	0x0b,	0x6b,	0x7b,	-0x1	},	insn_logicmem },
 	{ "tst",	{	0x0d,	0x6d,	0x7d,	-0x1	},	insn_gen0 },