# HG changeset patch
# User lost
# Date 1244776712 0
# Node ID 0df2a39a268c186ccd92bc9fadd51e6272c06f38
# Parent  59a138df0401a135e4a95728ddc19a1064a89e17
Added --6809/--6309 switches and some cleanups in error reporting

diff -r 59a138df0401 -r 0df2a39a268c ChangeLog
--- a/ChangeLog	Fri Jun 12 01:31:18 2009 +0000
+++ b/ChangeLog	Fri Jun 12 03:18:32 2009 +0000
@@ -22,6 +22,10 @@
 [+] Added COPY, COPY-, IMP, EXP, TFRP, TFRM, TFRS, TFRR as alternatives to
     the TFM instruction variations for compatibility with other assemblers
     [LWASM]
+[+] Added --6809/-9 switch to cause 6309 instructions to be rejected; also
+    included --6309/-3 switch to force default allow of 6309 instructions
+    [LWASM]
+[ ] Fixed a few cosmetic issues with error reporting
 
 Version 2.4
 
diff -r 59a138df0401 -r 0df2a39a268c lwasm/insn_indexed.c
--- a/lwasm/insn_indexed.c	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/insn_indexed.c	Fri Jun 12 03:18:32 2009 +0000
@@ -35,8 +35,10 @@
 
 void insn_indexed_aux(asmstate_t *as, lwasm_line_t *l, const char **p, int *b1, int *b2, int *b3)
 {
+	struct opvals { char *opstr; int pb; };
+	
 	static const char *regs = "X  Y  U  S  W  PCRPC ";
-	static const struct { char *opstr; int pb; } simpleindex[] =
+	static const struct opvals simpleindex[] =
 	{
 		{",x", 0x84},		{",y", 0xa4},		{",u", 0xc4},		{",s", 0xe4},
 		{",x+", 0x80},		{",y+", 0xa0},		{",u+", 0xc0},		{",s+", 0xe0},
@@ -64,12 +66,47 @@
 		
 		{ "", -1 }
 	};
+
+	static const char *regs9 = "X  Y  U  S     PCRPC ";
+	static const struct opvals simpleindex9[] =
+	{
+		{",x", 0x84},		{",y", 0xa4},		{",u", 0xc4},		{",s", 0xe4},
+		{",x+", 0x80},		{",y+", 0xa0},		{",u+", 0xc0},		{",s+", 0xe0},
+		{",x++", 0x81},		{",y++", 0xa1},		{",u++", 0xc1},		{",s++", 0xe1},
+		{",-x", 0x82},		{",-y", 0xa2},		{",-u", 0xc2},		{",-s", 0xe2},
+		{",--x", 0x83},		{",--y", 0xa3},		{",--u", 0xc3},		{",--s", 0xe3},
+		{"a,x", 0x86},		{"a,y", 0xa6},		{"a,u", 0xc6},		{"a,s", 0xe6},
+		{"b,x", 0x85},		{"b,y", 0xa5},		{"b,u", 0xc5},		{"b,s", 0xe5},
+		{"d,x", 0x8b},		{"d,y", 0xab},		{"d,u", 0xcb},		{"d,s", 0xed},
+		
+		{"[,x]", 0x94},		{"[,y]", 0xb4},		{"[,u", 0xd4},		{"[,s]", 0xf4},
+		{"[,x++]", 0x91},	{"[,y++]", 0xb1},	{"[,u++]", 0xd1},	{"[,s++]", 0xf1},
+		{"[,--x]", 0x93},	{"[,--y]", 0xb3},	{"[,--u]", 0xd3},	{"[,--s]", 0xf3},
+		{"[a,x]", 0x96},	{"[a,y]", 0xb6},	{"[a,u]", 0xd6},	{"[a,s]", 0xf6},
+		{"[b,x]", 0x95},	{"[b,y]", 0xb5},	{"[b,u]", 0xd5},	{"[b,s]", 0xf5},
+		{"[d,x]", 0x9b},	{"[d,y]", 0xbb},	{"[d,u]", 0xdb},	{"[d,s]", 0xfd},
+		
+		{ "", -1 }
+	};
 	char stbuf[25];
 	int i, j, rn;
 	int f8 = 0, f16 = 0, f0 = 0;
 	int r, v;
 	int indir = 0;
 	int fs8 = 0, fs16 = 0;
+	const struct opvals *simples;
+	const char *reglist;
+	
+	if (as -> no6309)
+	{
+		simples = simpleindex9;
+		reglist = regs9;
+	}
+	else
+	{
+		simples = simpleindex;
+		reglist = regs;
+	}
 	
 	// initialize output bytes
 	*b1 = *b2 = *b3 = -1;
@@ -88,14 +125,14 @@
 	if (!*((*p) + i) || isspace(*((*p) + i)))
 	{
 		// do simple lookup
-		for (j = 0; simpleindex[j].opstr[0]; j++)
+		for (j = 0; simples[j].opstr[0]; j++)
 		{
-			if (!strcasecmp(stbuf, simpleindex[j].opstr))
+			if (!strcasecmp(stbuf, simples[j].opstr))
 				break;
 		}
-		if (simpleindex[j].opstr[0])
+		if (simples[j].opstr[0])
 		{
-			*b1 = simpleindex[j].pb;
+			*b1 = simples[j].pb;
 			(*p) += i;
 			return;
 		}
@@ -189,7 +226,7 @@
 	}
 	
 	// now get the register
-	rn = lwasm_lookupreg3(regs, p);
+	rn = lwasm_lookupreg3(reglist, p);
 	if (rn < 0)
 	{
 		*b1 = 0;
diff -r 59a138df0401 -r 0df2a39a268c lwasm/insn_rtor.c
--- a/lwasm/insn_rtor.c	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/insn_rtor.c	Fri Jun 12 03:18:32 2009 +0000
@@ -31,13 +31,14 @@
 {
 	int r0, r1;
 	static const char *regs = "D X Y U S PCW V A B CCDP0 0 E F ";
-	
+	static const char *regs9 = "D X Y U S PC    A B CCDP        ";
+		
 	lwasm_emitop(as, l, instab[opnum].ops[0]);
 	// register to register (r0,r1)
 	// registers are in order:
 	// D,X,Y,U,S,PC,W,V
 	// A,B,CC,DP,0,0,E,F
-	r0 = lwasm_lookupreg2(regs, p);
+	r0 = lwasm_lookupreg2((as -> no6309) ? regs9 : regs, p);
 	if (r0 < 0 || *(*p)++ != ',')
 	{
 		register_error(as, l, 1, "Bad operand");
@@ -45,7 +46,7 @@
 	}
 	else
 	{
-		r1 = lwasm_lookupreg2(regs, p);
+		r1 = lwasm_lookupreg2((as -> no6309) ? regs9 : regs, p);
 		if (r1 < 0)
 		{
 			register_error(as, l, 1, "Bad operand");
diff -r 59a138df0401 -r 0df2a39a268c lwasm/instab.c
--- a/lwasm/instab.c	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/instab.c	Fri Jun 12 03:18:32 2009 +0000
@@ -88,53 +88,53 @@
 	{ "abx",	{	0x3a,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "adca",	{	0x99,	0xa9,	0xb9,	0x89	},	insn_gen8 },
 	{ "adcb",	{	0xd9,	0xe9,	0xf9,	0xc9	},	insn_gen8 },
-	{ "adcd",	{	0x1099,	0x10a9,	0x10b9,	0x1089	},	insn_gen16 },
-	{ "adcr",	{	0x1031,	-0x1,	-0x1,	-0x1	},	insn_rtor },
+	{ "adcd",	{	0x1099,	0x10a9,	0x10b9,	0x1089	},	insn_gen16 , 0, 0, 0, 1},
+	{ "adcr",	{	0x1031,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
 	{ "adda",	{	0x9b,	0xab,	0xbb,	0x8b	},	insn_gen8 },
 	{ "addb",	{	0xdb,	0xeb,	0xfb,	0xcb	},	insn_gen8 },
 	{ "addd",	{	0xd3,	0xe3,	0xf3,	0xc3	},	insn_gen16 },
-	{ "adde",	{	0x119b,	0x11ab,	0x11bb,	0x118b	},	insn_gen8 },
-	{ "addf",	{	0x11db,	0x11eb,	0x11fb,	0x11cb	},	insn_gen8 },
-	{ "addr",	{	0x1030,	-0x1,	-0x1,	-0x1	},	insn_rtor },
-	{ "addw",	{	0x109b,	0x10ab,	0x10bb,	0x108b	},	insn_gen16 },
-	{ "aim",	{	0x02,	0x62,	0x72,	-0x1	},	insn_logicmem },
+	{ "adde",	{	0x119b,	0x11ab,	0x11bb,	0x118b	},	insn_gen8, 0, 0, 0, 1 },
+	{ "addf",	{	0x11db,	0x11eb,	0x11fb,	0x11cb	},	insn_gen8, 0, 0, 0, 1 },
+	{ "addr",	{	0x1030,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
+	{ "addw",	{	0x109b,	0x10ab,	0x10bb,	0x108b	},	insn_gen16, 0, 0, 0, 1 },
+	{ "aim",	{	0x02,	0x62,	0x72,	-0x1	},	insn_logicmem, 0, 0, 0, 1 },
 	{ "anda",	{	0x94,	0xa4,	0xb4,	0x84	},	insn_gen8 },
 	{ "andb",	{	0xd4,	0xe4,	0xf4,	0xc4	},	insn_gen8 },
 	{ "andcc",	{	0x1c,	-0x1,	-0x1,	0x1c	},	insn_imm8 },
-	{ "andd",	{	0x1094,	0x10a4,	0x10b4,	0x1084	},	insn_gen16 },
-	{ "andr",	{	0x1034,	-0x1,	-0x1,	-0x1	},	insn_rtor },
+	{ "andd",	{	0x1094,	0x10a4,	0x10b4,	0x1084	},	insn_gen16, 0, 0, 0, 1 },
+	{ "andr",	{	0x1034,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
 	{ "asl",	{	0x08,	0x68,	0x78,	-0x1	},	insn_gen0 },
 	{ "asla",	{	0x48,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "aslb",	{	0x58,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "asld",	{	0x1048,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "asld",	{	0x1048,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "asr",	{	0x07,	0x67,	0x77,	-0x1	},	insn_gen0 },
 	{ "asra",	{	0x47,	-0x1,	-0x1,	-0x1	}, 	insn_inh },
 	{ "asrb",	{	0x57,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "asrd",	{	0x1047,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "asrd",	{	0x1047,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	
-	{ "band",	{	0x1130,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
+	{ "band",	{	0x1130,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
 	{ "bcc",	{	0x24,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bcs",	{	0x25,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
-	{ "beor",	{	0x1134,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
+	{ "beor",	{	0x1134,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
 	{ "beq",	{	0x27,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bge",	{	0x2c,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bgt",	{	0x2e,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bhi",	{	0x22,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bhs",	{	0x24,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
-	{ "biand",	{	0x1131,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
-	{ "bieor",	{	0x1135,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
-	{ "bior",	{	0x1133, -0x1,	-0x1,	-0x1	},	insn_bitbit },
+	{ "biand",	{	0x1131,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
+	{ "bieor",	{	0x1135,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
+	{ "bior",	{	0x1133, -0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
 	{ "bita",	{	0x95,	0xa5,	0xb5,	0x85	},	insn_gen8 },
 	{ "bitb",	{	0xd5,	0xe5,	0xf5,	0xc5	},	insn_gen8 },
-	{ "bitd",	{	0x1095,	0x10a5,	0x10b5,	0x1085	},	insn_gen16 },
-	{ "bitmd",	{	0x113c, -0x1,	-0x1,	0x113c	},	insn_imm8 },
+	{ "bitd",	{	0x1095,	0x10a5,	0x10b5,	0x1085	},	insn_gen16, 0, 0, 0, 1 },
+	{ "bitmd",	{	0x113c, -0x1,	-0x1,	0x113c	},	insn_imm8, 0, 0, 0, 1 },
 	{ "ble",	{	0x2f,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "blo",	{	0x25,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bls",	{	0x23,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "blt",	{	0x2d,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bmi",	{	0x2b,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bne",	{	0x26, 	-0x1,	-0x1,	-0x1	},	insn_rel8 },
-	{ "bor",	{	0x1132,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
+	{ "bor",	{	0x1132,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
 	{ "bpl",	{	0x2a,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "bra",	{	0x20,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
 	{ "brn",	{	0x21,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
@@ -145,55 +145,55 @@
 	{ "clr",	{	0x0f,	0x6f,	0x7f,	-0x1	},	insn_gen0 },
 	{ "clra",	{	0x4f,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "clrb",	{	0x5f,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "clrd",	{	0x104f,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "clre",	{	0x114f,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "clrf",	{	0x115f,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "clrw",	{	0x105f,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "clrd",	{	0x104f,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "clre",	{	0x114f,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "clrf",	{	0x115f,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "clrw",	{	0x105f,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "cmpa",	{	0x91,	0xa1,	0xb1,	0x81	},	insn_gen8 },
 	{ "cmpb",	{	0xd1,	0xe1,	0xf1,	0xc1	},	insn_gen8 },
 	{ "cmpd",	{	0x1093,	0x10a3,	0x10b3,	0x1083	},	insn_gen16 },
-	{ "cmpe",	{	0x1191,	0x11a1,	0x11b1,	0x1181	},	insn_gen8 },
-	{ "cmpf",	{	0x11d1,	0x11e1,	0x11f1,	0x11c1	},	insn_gen8 },
-	{ "cmpr",	{	0x1037,	-0x1,	-0x1,	-0x1	},	insn_rtor },
+	{ "cmpe",	{	0x1191,	0x11a1,	0x11b1,	0x1181	},	insn_gen8, 0, 0, 0, 1 },
+	{ "cmpf",	{	0x11d1,	0x11e1,	0x11f1,	0x11c1	},	insn_gen8, 0, 0, 0, 1 },
+	{ "cmpr",	{	0x1037,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
 	{ "cmps",	{	0x119c,	0x11ac,	0x11bc,	0x118c	},	insn_gen16 },
 	{ "cmpu",	{	0x1193,	0x11a3,	0x11b3,	0x1183	},	insn_gen16 },
-	{ "cmpw",	{	0x1091,	0x10a1,	0x10b1,	0x1081	},	insn_gen16 },
+	{ "cmpw",	{	0x1091,	0x10a1,	0x10b1,	0x1081	},	insn_gen16, 0, 0, 0, 1 },
 	{ "cmpx",	{	0x9c,	0xac,	0xbc,	0x8c	}, 	insn_gen16 },
 	{ "cmpy",	{	0x109c,	0x10ac,	0x10bc,	0x108c	},	insn_gen16 },
 	{ "com",	{	0x03,	0x63,	0x73,	-0x1	},	insn_gen0 },
 	{ "coma",	{	0x43,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "comb",	{	0x53,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "comd",	{	0x1043,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "come",	{	0x1143,	-0x1, 	-0x1,	-0x1	},	insn_inh },
-	{ "comf", 	{	0x1153, -0x1,	-0x1,	-0x1	}, 	insn_inh },
-	{ "comw",	{	0x1053,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "comd",	{	0x1043,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "come",	{	0x1143,	-0x1, 	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "comf", 	{	0x1153, -0x1,	-0x1,	-0x1	}, 	insn_inh, 0, 0, 0, 1 },
+	{ "comw",	{	0x1053,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "cwai",	{	0x3c, 	-0x1,	-0x1,	-0x1	},	insn_imm8 },
 	
 	{ "daa",	{	0x19,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "dec",	{	0x0a,	0x6a,	0x7a,	-0x1	},	insn_gen0 },
 	{ "deca",	{	0x4a,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "decb",	{	0x5a,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "decd",	{	0x104a,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "dece",	{	0x114a,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "decf",	{	0x115a,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "decw",	{	0x105a,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "divd",	{	0x118d,	0x119d,	0x11ad,	0x11bd	},	insn_gen8 },
-	{ "divq",	{	0x118e,	0x119e,	0x11ae,	0x11be	},	insn_gen16 },
+	{ "decd",	{	0x104a,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "dece",	{	0x114a,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "decf",	{	0x115a,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "decw",	{	0x105a,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "divd",	{	0x118d,	0x119d,	0x11ad,	0x11bd	},	insn_gen8, 0, 0, 0, 1 },
+	{ "divq",	{	0x118e,	0x119e,	0x11ae,	0x11be	},	insn_gen16, 0, 0, 0, 1 },
 
-	{ "eim",	{	0x05,	0x65,	0x75,	-0x1	},	insn_logicmem },
+	{ "eim",	{	0x05,	0x65,	0x75,	-0x1	},	insn_logicmem, 0, 0, 0, 1 },
 	{ "eora",	{	0x98,	0xa8,	0xb8,	0x88	},	insn_gen8 },
 	{ "eorb",	{	0xd8,	0xe9,	0xf9,	0xc8	},	insn_gen8 },
-	{ "eord",	{	0x1098,	0x10a8,	0x10b8,	0x1088	},	insn_gen16 },
-	{ "eorr",	{	0x1036,	-0x1,	-0x1,	-0x1	},	insn_rtor },
+	{ "eord",	{	0x1098,	0x10a8,	0x10b8,	0x1088	},	insn_gen16, 0, 0, 0, 1 },
+	{ "eorr",	{	0x1036,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
 	{ "exg",	{	0x1e,	-0x1,	-0x1,	-0x1	},	insn_rtor },
 	
 	{ "inc",	{	0x0c,	0x6c,	0x7c,	-0x1	},	insn_gen0 },
 	{ "inca",	{	0x4c,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "incb",	{	0x5c,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "incd",	{	0x104c,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "ince",	{	0x114c,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "incf",	{	0x115c,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "incw",	{	0x105c,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "incd",	{	0x104c,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "ince",	{	0x114c,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "incf",	{	0x115c,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "incw",	{	0x105c,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	
 	{ "jmp",	{	0x0e,	0x6e,	0x7e,	-0x1	},	insn_gen0 },
 	{ "jsr",	{	0x9d,	0xad,	0xbd,	-0x1	}, 	insn_gen0 },
@@ -219,17 +219,17 @@
 	{ "lbvs",	{	0x1029,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
 	{ "lda",	{	0x96,	0xa6,	0xb6,	0x86	},	insn_gen8 },
 	{ "ldb",	{	0xd6,	0xe6,	0xf6,	0xc6	},	insn_gen8 },
-	{ "ldbt",	{	0x1136,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
+	{ "ldbt",	{	0x1136,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
 	{ "ldd",	{	0xdc,	0xec,	0xfc,	0xcc	},	insn_gen16 },
-	{ "lde",	{	0x1196,	0x11a6,	0x11b6,	0x1186	},	insn_gen8 },
-	{ "ldf",	{	0x11d6,	0x11e6,	0x11f6,	0x11c6	},	insn_gen8 },
-	{ "ldq",	{	0x10dc,	0x10ec,	0x10fc,	0xcd	},	insn_gen32 },
+	{ "lde",	{	0x1196,	0x11a6,	0x11b6,	0x1186	},	insn_gen8, 0, 0, 0, 1 },
+	{ "ldf",	{	0x11d6,	0x11e6,	0x11f6,	0x11c6	},	insn_gen8, 0, 0, 0, 1 },
+	{ "ldq",	{	0x10dc,	0x10ec,	0x10fc,	0xcd	},	insn_gen32, 0, 0, 0, 1 },
 	{ "lds",	{	0x10de,	0x10ee,	0x10fe,	0x10ce	},	insn_gen16 },
 	{ "ldu",	{ 	0xde,	0xee,	0xfe,	0xce	},	insn_gen16 },
-	{ "ldw",	{	0x1096,	0x10a6,	0x10b6,	0x1086	},	insn_gen16 },
+	{ "ldw",	{	0x1096,	0x10a6,	0x10b6,	0x1086	},	insn_gen16, 0, 0, 0, 1 },
 	{ "ldx",	{	0x9e,	0xae,	0xbe,	0x8e	},	insn_gen16 },
 	{ "ldy",	{	0x109e,	0x10ae,	0x10be,	0x108e	},	insn_gen16 },
-	{ "ldmd",	{	0x113d, -0x1,	-0x1,	0x113d	},	insn_imm8 },
+	{ "ldmd",	{	0x113d, -0x1,	-0x1,	0x113d	},	insn_imm8, 0, 0, 0, 1 },
 	{ "leas",	{	0x32,	-0x1,	-0x1,	-0x1	},	insn_indexed },
 	{ "leau",	{	0x33,	-0x1,	-0x1,	-0x1	},	insn_indexed },
 	{ "leax",	{	0x30,	-0x1,	-0x1,	-0x1	},	insn_indexed },
@@ -237,106 +237,106 @@
 	{ "lsl",	{	0x08,	0x68,	0x78,	-0x1	},	insn_gen0 },
 	{ "lsla",	{	0x48,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "lslb",	{	0x58,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "lsld",	{	0x1048,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "lsld",	{	0x1048,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "lsr",	{	0x04,	0x64,	0x74,	-0x1	},	insn_gen0 },
 	{ "lsra",	{	0x44,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "lsrb",	{	0x54,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "lsrd",	{	0x1044,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "lsrw",	{	0x1054,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "lsrd",	{	0x1044,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "lsrw",	{	0x1054,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 
 	{ "mul",	{	0x3d,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "muld",	{	0x118f,	0x119f,	0x11af,	0x11bf	},	insn_gen16 },
+	{ "muld",	{	0x118f,	0x119f,	0x11af,	0x11bf	},	insn_gen16, 0, 0, 0, 1 },
 	
 	{ "neg",	{	0x00,	0x60,	0x70,	-0x1	},	insn_gen0 },
 	{ "nega",	{	0x40,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "negb",	{	0x50,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "negd",	{	0x1040,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "negd",	{	0x1040,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "nop",	{	0x12,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	
-	{ "oim",	{	0x01,	0x61,	0x71,	-0x1	},	insn_logicmem },
+	{ "oim",	{	0x01,	0x61,	0x71,	-0x1	},	insn_logicmem, 0, 0, 0, 1 },
 	{ "ora",	{	0x9a,	0xaa,	0xba,	0x8a	},	insn_gen8 },
 	{ "orb",	{	0xda,	0xea,	0xfa,	0xca	},	insn_gen8 },
 	{ "orcc",	{	0x1a,	-0x1,	-0x1,	0x1a	},	insn_imm8 },
-	{ "ord",	{	0x109a,	0x10aa,	0x10ba,	0x108a	},	insn_gen16 },
-	{ "orr",	{	0x1035,	-0x1,	-0x1,	-0x1	},	insn_rtor },
+	{ "ord",	{	0x109a,	0x10aa,	0x10ba,	0x108a	},	insn_gen16, 0, 0, 0, 1 },
+	{ "orr",	{	0x1035,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
 	
 	{ "pshs",	{	0x34,	-0x1,	-0x1,	-0x1	},	insn_rlist },
-	{ "pshsw",	{	0x1038,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "pshsw",	{	0x1038,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "pshu",	{	0x36,	-0x1,	-0x1,	-0x1	},	insn_rlist },
-	{ "pshuw",	{	0x103a,	-0x1,	-0x1,	-0x1	},	insn_inh	},
+	{ "pshuw",	{	0x103a,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1	},
 	{ "puls",	{	0x35,	-0x1,	-0x1,	-0x1	},	insn_rlist },
-	{ "pulsw",	{	0x1039,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "pulsw",	{	0x1039,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "pulu",	{	0x37,	-0x1,	-0x1,	-0x1	},	insn_rlist },
-	{ "puluw",	{	0x103b,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "puluw",	{	0x103b,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	
 	{ "rol",	{	0x09,	0x69,	0x79,	-0x1	},	insn_gen0 },
 	{ "rola",	{	0x49,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "rolb",	{	0x59,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "rold",	{	0x1049,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "rolw",	{	0x1059,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "rold",	{	0x1049,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "rolw",	{	0x1059,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "ror",	{	0x06,	0x66,	0x76,	-0x1	},	insn_gen0 },
 	{ "rora",	{	0x46,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "rorb",	{	0x56,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "rord",	{	0x1046,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "rorw",	{	0x1056,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "rord",	{	0x1046,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "rorw",	{	0x1056,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "rti",	{	0x3b,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "rts",	{	0x39,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	
 	{ "sbca",	{	0x92,	0xa2,	0xb2,	0x82	},	insn_gen8 },
 	{ "sbcb",	{	0xd2,	0xe2,	0xf2,	0xc2	},	insn_gen8 },
-	{ "sbcd",	{	0x1092,	0x10a2,	0x10b2,	0x1082	},	insn_gen16 },
-	{ "sbcr",	{	0x1033,	-0x1,	-0x1,	-0x1	},	insn_rtor },
+	{ "sbcd",	{	0x1092,	0x10a2,	0x10b2,	0x1082	},	insn_gen16, 0, 0, 0, 1 },
+	{ "sbcr",	{	0x1033,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
 	{ "sex",	{	0x1d,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "sexw",	{	0x14,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "sexw",	{	0x14,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 	{ "sta",	{	0x97,	0xa7,	0xb7,	-0x1	},	insn_gen0 },
 	{ "stb",	{	0xd7,	0xe7,	0xf7,	-0x1	},	insn_gen0 },
-	{ "stbt",	{	0x1137,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
+	{ "stbt",	{	0x1137,	-0x1,	-0x1,	-0x1	},	insn_bitbit, 0, 0, 0, 1 },
 	{ "std",	{	0xdd,	0xed,	0xfd,	-0x1	},	insn_gen0 },
-	{ "ste",	{	0x1197,	0x11a7,	0x11b7,	-0x1	},	insn_gen0 },
-	{ "stf",	{	0x11d7,	0x11e7,	0x11f7,	-0x1	},	insn_gen0 },
-	{ "stq",	{	0x10dd,	0x10ed,	0x10fd,	-0x1	},	insn_gen0 },
+	{ "ste",	{	0x1197,	0x11a7,	0x11b7,	-0x1	},	insn_gen0, 0, 0, 0, 1 },
+	{ "stf",	{	0x11d7,	0x11e7,	0x11f7,	-0x1	},	insn_gen0, 0, 0, 0, 1 },
+	{ "stq",	{	0x10dd,	0x10ed,	0x10fd,	-0x1	},	insn_gen0, 0, 0, 0, 1 },
 	{ "sts",	{	0x10df,	0x10ef,	0x10ff,	-0x1	},	insn_gen0 },
 	{ "stu",	{	0xdf,	0xef,	0xff,	-0x1	},	insn_gen0 },
-	{ "stw",	{	0x1097,	0x10a7,	0x10b7,	-0x1	},	insn_gen0 },
+	{ "stw",	{	0x1097,	0x10a7,	0x10b7,	-0x1	},	insn_gen0, 0, 0, 0, 1 },
 	{ "stx",	{	0x9f,	0xaf,	0xbf,	-0x1	},	insn_gen0 },
 	{ "sty",	{	0x109f,	0x10af,	0x10bf,	-0x1	},	insn_gen0 },
 	{ "suba",	{	0x90,	0xa0,	0xb0,	0x80	},	insn_gen8 },
 	{ "subb",	{	0xd0,	0xe0,	0xf0,	0xc0	},	insn_gen8 },
 	{ "subd",	{	0x93,	0xa3,	0xb3,	0x83	},	insn_gen16 },
-	{ "sube",	{	0x1190,	0x11a0,	0x11b0,	0x1180	},	insn_gen8 },
-	{ "subf",	{	0x11d0,	0x11e0,	0x11f0,	0x11c0	},	insn_gen8 },
-	{ "subr",	{	0x1032,	-0x1,	-0x1,	-0x1	},	insn_rtor },
-	{ "subw",	{	0x1090,	0x10a0,	0x1090,	0x1080	},	insn_gen8 },
+	{ "sube",	{	0x1190,	0x11a0,	0x11b0,	0x1180	},	insn_gen8, 0, 0, 0, 1 },
+	{ "subf",	{	0x11d0,	0x11e0,	0x11f0,	0x11c0	},	insn_gen8, 0, 0, 0, 1 },
+	{ "subr",	{	0x1032,	-0x1,	-0x1,	-0x1	},	insn_rtor, 0, 0, 0, 1 },
+	{ "subw",	{	0x1090,	0x10a0,	0x1090,	0x1080	},	insn_gen8, 0, 0, 0, 1 },
 	{ "swi",	{	0x3f,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "swi2",	{	0x103f,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "swi3",	{	0x113f,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "sync",	{	0x13,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	
 	// note: 		r+,r+	r-,r-	r+,r	r,r+
-	{ "tfm",	{	0x1138,	0x1139,	0x113a,	0x113b	},	insn_tfm },
+	{ "tfm",	{	0x1138,	0x1139,	0x113a,	0x113b	},	insn_tfm, 0, 0, 0, 1 },
 
 	// compatibility opcodes for tfm in other assemblers
-	{ "copy",	{	0x1138, -1, -1, -1},	insn_tfmrtor },
-	{ "tfrp",	{	0x1138, -1, -1, -1},	insn_tfmrtor },
+	{ "copy",	{	0x1138, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
+	{ "tfrp",	{	0x1138, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
 	
-	{ "copy-",	{	0x1139, -1, -1, -1},	insn_tfmrtor },
-	{ "tfrm",	{	0x1139, -1, -1, -1},	insn_tfmrtor },
+	{ "copy-",	{	0x1139, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
+	{ "tfrm",	{	0x1139, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
 	
-	{ "imp",	{	0x113a, -1, -1, -1},	insn_tfmrtor },
-	{ "tfrs",	{	0x113a, -1, -1, -1},	insn_tfmrtor },
+	{ "imp",	{	0x113a, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
+	{ "tfrs",	{	0x113a, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
 	
-	{ "exp",	{	0x113b, -1, -1, -1},	insn_tfmrtor },
-	{ "tfrr",	{	0x113b, -1, -1, -1},	insn_tfmrtor },
+	{ "exp",	{	0x113b, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
+	{ "tfrr",	{	0x113b, -1, -1, -1},	insn_tfmrtor, 0, 0, 0, 1 },
 
 	{ "tfr",	{	0x1f,	-0x1,	-0x1,	-0x1	},	insn_rtor },
-	{ "tim",	{	0x0b,	0x6b,	0x7b,	-0x1	},	insn_logicmem },
+	{ "tim",	{	0x0b,	0x6b,	0x7b,	-0x1	},	insn_logicmem, 0, 0, 0, 1 },
 	{ "tst",	{	0x0d,	0x6d,	0x7d,	-0x1	},	insn_gen0 },
 	{ "tsta",	{	0x4d,	-0x1,	-0x1,	-0x1	},	insn_inh },
 	{ "tstb",	{	0x5d,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "tstd",	{	0x104d,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "tste",	{	0x114d,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "tstf",	{	0x115d,	-0x1,	-0x1,	-0x1	},	insn_inh },
-	{ "tstw",	{	0x105d,	-0x1,	-0x1,	-0x1	},	insn_inh },
+	{ "tstd",	{	0x104d,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "tste",	{	0x114d,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "tstf",	{	0x115d,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
+	{ "tstw",	{	0x105d,	-0x1,	-0x1,	-0x1	},	insn_inh, 0, 0, 0, 1 },
 
 	{ "org",	{ -1, -1, -1, -1 },	pseudo_org },
 
diff -r 59a138df0401 -r 0df2a39a268c lwasm/instab.h
--- a/lwasm/instab.h	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/instab.h	Fri Jun 12 03:18:32 2009 +0000
@@ -34,6 +34,7 @@
 	int iscond;					/* set if this should be dispatched even if skipping a condition/macro */
 	int endm;					/* end of macro? */
 	int setsym;					/* does this set a symbol address? EQU, SET */
+	int is6309;					/* is this 6309 only? */
 } instab_t;
 
 #define OPFUNC(fn)	void (fn)(asmstate_t *as, lwasm_line_t *l, char **p, int opnum)
diff -r 59a138df0401 -r 0df2a39a268c lwasm/lwasm.h
--- a/lwasm/lwasm.h	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/lwasm.h	Fri Jun 12 03:18:32 2009 +0000
@@ -180,6 +180,9 @@
 	// items used only for the "object" target
 	sectiontab_t *sections;		// pointer to section table
 	sectiontab_t *csect;		// current section - NULL if not in one
+	
+	// only 6809 ops?
+	int no6309;					
 } asmstate_t;
 
 // do not rewrite XXX,r to ,r if XXX evaluates to 0
diff -r 59a138df0401 -r 0df2a39a268c lwasm/main.c
--- a/lwasm/main.c	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/main.c	Fri Jun 12 03:18:32 2009 +0000
@@ -112,6 +112,14 @@
 		}
 		break;
 
+	case '9':
+		as -> no6309 = 1;
+		break;
+	
+	case '3':
+		as -> no6309 = 0;
+		break;
+
 	case ARGP_KEY_END:
 		// done; sanity check
 		if (!as -> outfile)
@@ -149,6 +157,10 @@
 				"Generate proprietary object file format for later linking, equivalent of --format=obj" },
 	{ "pragma",		'p',	"PRAGMA",	0,
 				"Set an assembler pragma to any value understood by the \"pragma\" pseudo op"},
+	{ "6809",		'9',	0,			0,
+				"Set assembler to 6809 only mode" },
+	{ "6309",		'3',	0,			0,
+				"Set assembler to 6309 mode (default)" },
 	{ 0 }
 };
 
diff -r 59a138df0401 -r 0df2a39a268c lwasm/parse.c
--- a/lwasm/parse.c	Fri Jun 12 01:31:18 2009 +0000
+++ b/lwasm/parse.c	Fri Jun 12 03:18:32 2009 +0000
@@ -181,18 +181,21 @@
 	// an operation code; otherwise, call the operation function
 	if (instab[opnum].opcode)
 	{
-		if (instab[opnum].fn)
+		if (instab[opnum].fn && !(as -> no6309 && instab[opnum].is6309))
 		{
 			(instab[opnum].fn)(as, l, &p2, opnum);
 			
 			// if we didn't end on a "space" character or EOL, throw error
-			if (*p2 && !isspace(*p2))
+			if (*p2 && !isspace(*p2) && !(l -> err))
 				register_error(as, l, 1, "Bad operand");
 		}
 		else
 		{
 			// carp about unimplemented operation
-			register_error(as, l, 1, "Unimplemented operation code: %s", opc);
+			if (instab[opnum].is6309)
+				register_error(as, l, 1, "Use of 6309 operation code: %s", opc);
+			else
+				register_error(as, l, 1, "Unimplemented operation code: %s", opc);
 		}
 	}
 	else