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Added ifdef/ifndef conditionals
author lost
date Sun, 25 Jan 2009 04:02:50 +0000
parents 6097cb1486f8
children
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/*
instab.c
Copyright © 2008 William Astle

This file is part of LWASM.

LWASM is free software: you can redistribute it and/or modify it under the
terms of the GNU General Public License as published by the Free Software
Foundation, either version 3 of the License, or (at your option) any later
version.

This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.

You should have received a copy of the GNU General Public License along with
this program. If not, see <http://www.gnu.org/licenses/>.


Contains the instruction table for assembling code
*/

#include <stdlib.h>

#define __instab_c_seen__
#include "instab.h"

extern OPFUNC(insn_inh);
extern OPFUNC(insn_gen8);
extern OPFUNC(insn_gen16);
extern OPFUNC(insn_gen32);
extern OPFUNC(insn_gen0);
extern OPFUNC(insn_rtor);
extern OPFUNC(insn_imm8);
extern OPFUNC(insn_rel8);
extern OPFUNC(insn_rel16);
extern OPFUNC(insn_rlist);
extern OPFUNC(insn_bitbit);
extern OPFUNC(insn_logicmem);
extern OPFUNC(insn_tfm);
extern OPFUNC(insn_indexed);

extern OPFUNC(pseudo_org);
extern OPFUNC(pseudo_equ);
extern OPFUNC(pseudo_rmb);
extern OPFUNC(pseudo_rmd);
extern OPFUNC(pseudo_rmq);
extern OPFUNC(pseudo_zmb);
extern OPFUNC(pseudo_zmd);
extern OPFUNC(pseudo_zmq);
extern OPFUNC(pseudo_include);
extern OPFUNC(pseudo_end);
extern OPFUNC(pseudo_align);
extern OPFUNC(pseudo_error);
extern OPFUNC(pseudo_fcc);
extern OPFUNC(pseudo_fcs);
extern OPFUNC(pseudo_fcn);
extern OPFUNC(pseudo_fcb);
extern OPFUNC(pseudo_fdb);
extern OPFUNC(pseudo_fqb);
extern OPFUNC(pseudo_ifne);
extern OPFUNC(pseudo_ifeq);
extern OPFUNC(pseudo_ifgt);
extern OPFUNC(pseudo_ifge);
extern OPFUNC(pseudo_iflt);
extern OPFUNC(pseudo_ifle);
extern OPFUNC(pseudo_else);
extern OPFUNC(pseudo_endc);
extern OPFUNC(pseudo_macro);
extern OPFUNC(pseudo_endm);
extern OPFUNC(pseudo_setdp);
extern OPFUNC(pseudo_set);
extern OPFUNC(pseudo_section);
extern OPFUNC(pseudo_endsection);
extern OPFUNC(pseudo_pragma);
extern OPFUNC(pseudo_starpragma);
extern OPFUNC(pseudo_extern);
extern OPFUNC(pseudo_export);
extern OPFUNC(pseudo_ifdef);
extern OPFUNC(pseudo_ifndef);

instab_t instab[] =
{
	{ "abx",	{	0x3a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "adca",	{	0x99,	0xa9,	0xb9,	0x89	},	insn_gen8 },
	{ "adcb",	{	0xd9,	0xe9,	0xf9,	0xc9	},	insn_gen8 },
	{ "adcd",	{	0x1099,	0x10a9,	0x10b9,	0x1089	},	insn_gen16 },
	{ "adcr",	{	0x1031,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "adda",	{	0x9b,	0xab,	0xbb,	0x8b	},	insn_gen8 },
	{ "addb",	{	0xdb,	0xeb,	0xfb,	0xcb	},	insn_gen8 },
	{ "addd",	{	0xd3,	0xe3,	0xf3,	0xc3	},	insn_gen16 },
	{ "adde",	{	0x119b,	0x11ab,	0x11bb,	0x118b	},	insn_gen8 },
	{ "addf",	{	0x11db,	0x11eb,	0x11fb,	0x11cb	},	insn_gen8 },
	{ "addr",	{	0x1030,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "addw",	{	0x109b,	0x10ab,	0x10bb,	0x108b	},	insn_gen16 },
	{ "aim",	{	0x02,	0x62,	0x72,	-0x1	},	insn_logicmem },
	{ "anda",	{	0x94,	0xa4,	0xb4,	0x84	},	insn_gen8 },
	{ "andb",	{	0xd4,	0xe4,	0xf4,	0xc4	},	insn_gen8 },
	{ "andcc",	{	0x1c,	-0x1,	-0x1,	0x1c	},	insn_imm8 },
	{ "andd",	{	0x1094,	0x10a4,	0x10b4,	0x1084	},	insn_gen16 },
	{ "andr",	{	0x1034,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "asl",	{	0x08,	0x68,	0x78,	-0x1	},	insn_gen0 },
	{ "asla",	{	0x48,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "aslb",	{	0x58,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "asld",	{	0x1048,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "asr",	{	0x07,	0x67,	0x77,	-0x1	},	insn_gen0 },
	{ "asra",	{	0x47,	-0x1,	-0x1,	-0x1	}, 	insn_inh },
	{ "asrb",	{	0x57,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "asrd",	{	0x1047,	-0x1,	-0x1,	-0x1	},	insn_inh },
	
	{ "band",	{	0x1130,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "bcc",	{	0x24,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bcs",	{	0x25,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "beor",	{	0x1134,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "beq",	{	0x27,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bge",	{	0x2c,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bgt",	{	0x2e,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bhi",	{	0x22,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bhs",	{	0x24,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "biand",	{	0x1131,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "bieor",	{	0x1135,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "bior",	{	0x1133, -0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "bita",	{	0x95,	0xa5,	0xb5,	0x85	},	insn_gen8 },
	{ "bitb",	{	0xd5,	0xe5,	0xf5,	0xc5	},	insn_gen8 },
	{ "bitd",	{	0x1095,	0x10a5,	0x10b5,	0x1085	},	insn_gen16 },
	{ "bitmd",	{	0x113c, -0x1,	-0x1,	0x113c	},	insn_imm8 },
	{ "ble",	{	0x2f,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "blo",	{	0x25,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bls",	{	0x23,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "blt",	{	0x2d,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bmi",	{	0x2b,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bne",	{	0x26, 	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bor",	{	0x1132,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "bpl",	{	0x2a,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bra",	{	0x20,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "brn",	{	0x21,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bsr",	{	0x8d,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bvc",	{	0x28,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	{ "bvs",	{	0x29,	-0x1,	-0x1,	-0x1	},	insn_rel8 },
	
	{ "clr",	{	0x0f,	0x6f,	0x7f,	-0x1	},	insn_gen0 },
	{ "clra",	{	0x4f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "clrb",	{	0x5f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "clrd",	{	0x104f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "clre",	{	0x114f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "clrf",	{	0x115f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "clrw",	{	0x105f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "cmpa",	{	0x91,	0xa1,	0xb1,	0x81	},	insn_gen8 },
	{ "cmpb",	{	0xd1,	0xe1,	0xf1,	0xc1	},	insn_gen8 },
	{ "cmpd",	{	0x1093,	0x10a3,	0x10b3,	0x1083	},	insn_gen16 },
	{ "cmpe",	{	0x1191,	0x11a1,	0x11b1,	0x1181	},	insn_gen8 },
	{ "cmpf",	{	0x11d1,	0x11e1,	0x11f1,	0x11c1	},	insn_gen8 },
	{ "cmpr",	{	0x1037,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "cmps",	{	0x119c,	0x11ac,	0x11bc,	0x118c	},	insn_gen16 },
	{ "cmpu",	{	0x1193,	0x11a3,	0x11b3,	0x1183	},	insn_gen16 },
	{ "cmpw",	{	0x1091,	0x10a1,	0x10b1,	0x1081	},	insn_gen16 },
	{ "cmpx",	{	0x9c,	0xac,	0xbc,	0x8c	}, 	insn_gen16 },
	{ "cmpy",	{	0x109c,	0x10ac,	0x10bc,	0x108c	},	insn_gen16 },
	{ "com",	{	0x03,	0x63,	0x73,	-0x1	},	insn_gen0 },
	{ "coma",	{	0x43,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "comb",	{	0x53,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "comd",	{	0x1043,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "come",	{	0x1143,	-0x1, 	-0x1,	-0x1	},	insn_inh },
	{ "comf", 	{	0x1153, -0x1,	-0x1,	-0x1	}, 	insn_inh },
	{ "comw",	{	0x1053,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "cwai",	{	0x3c, 	-0x1,	-0x1,	-0x1	},	insn_imm8 },
	
	{ "daa",	{	0x19,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "dec",	{	0x0a,	0x6a,	0x7a,	-0x1	},	insn_gen0 },
	{ "deca",	{	0x4a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "decb",	{	0x5a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "decd",	{	0x104a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "dece",	{	0x114a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "decf",	{	0x115a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "decw",	{	0x105a,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "divd",	{	0x118d,	0x119d,	0x11ad,	0x11bd	},	insn_gen8 },
	{ "divq",	{	0x118e,	0x119e,	0x11ae,	0x11be	},	insn_gen16 },

	{ "eim",	{	0x05,	0x65,	0x75,	-0x1	},	insn_logicmem },
	{ "eora",	{	0x98,	0xa8,	0xb8,	0x88	},	insn_gen8 },
	{ "eorb",	{	0xd8,	0xe9,	0xf9,	0xc8	},	insn_gen8 },
	{ "eord",	{	0x1098,	0x10a8,	0x10b8,	0x1088	},	insn_gen16 },
	{ "eorr",	{	0x1036,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "exg",	{	0x1e,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	
	{ "inc",	{	0x0c,	0x6c,	0x7c,	-0x1	},	insn_gen0 },
	{ "inca",	{	0x4c,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "incb",	{	0x5c,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "incd",	{	0x104c,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "ince",	{	0x114c,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "incf",	{	0x115c,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "incw",	{	0x105c,	-0x1,	-0x1,	-0x1	},	insn_inh },
	
	{ "jmp",	{	0x0e,	0x6e,	0x7e,	-0x1	},	insn_gen0 },
	{ "jsr",	{	0x9d,	0xad,	0xbd,	-0x1	}, 	insn_gen0 },
	
	{ "lbcc",	{	0x1024,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbcs",	{	0x1025,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbeq",	{	0x1027,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbge",	{	0x102c,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbgt",	{	0x102e,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbhi",	{	0x1022,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbhs",	{	0x1024,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lble",	{	0x102f,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lblo",	{	0x1025,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbls",	{	0x1023,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lblt",	{	0x102d, -0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbmi",	{	0x102b,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbne",	{	0x1026,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbpl",	{	0x102a,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbra",	{	0x16,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbrn",	{	0x1021,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbsr",	{	0x17,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbvc",	{	0x1028,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lbvs",	{	0x1029,	-0x1,	-0x1,	-0x1	},	insn_rel16 },
	{ "lda",	{	0x96,	0xa6,	0xb6,	0x86	},	insn_gen8 },
	{ "ldb",	{	0xd6,	0xe6,	0xf6,	0xc6	},	insn_gen8 },
	{ "ldbt",	{	0x1136,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "ldd",	{	0xdc,	0xec,	0xfc,	0xcc	},	insn_gen16 },
	{ "lde",	{	0x1196,	0x11a6,	0x11b6,	0x1186	},	insn_gen8 },
	{ "ldf",	{	0x11d6,	0x11e6,	0x11f6,	0x11c6	},	insn_gen8 },
	{ "ldq",	{	0x10dc,	0x10ec,	0x10fc,	0xcd	},	insn_gen32 },
	{ "lds",	{	0x10de,	0x10ee,	0x10fe,	0x10ce	},	insn_gen16 },
	{ "ldu",	{ 	0xde,	0xee,	0xfe,	0xce	},	insn_gen16 },
	{ "ldw",	{	0x1096,	0x10a6,	0x10b6,	0x1086	},	insn_gen16 },
	{ "ldx",	{	0x9e,	0xae,	0xbe,	0x8e	},	insn_gen16 },
	{ "ldy",	{	0x109e,	0x10ae,	0x10be,	0x108e	},	insn_gen16 },
	{ "ldmd",	{	0x113d, -0x1,	-0x1,	0x113d	},	insn_imm8 },
	{ "leas",	{	0x32,	-0x1,	-0x1,	-0x1	},	insn_indexed },
	{ "leau",	{	0x33,	-0x1,	-0x1,	-0x1	},	insn_indexed },
	{ "leax",	{	0x30,	-0x1,	-0x1,	-0x1	},	insn_indexed },
	{ "leay",	{	0x31,	-0x1,	-0x1,	-0x1	},	insn_indexed },
	{ "lsl",	{	0x08,	0x68,	0x78,	-0x1	},	insn_gen0 },
	{ "lsla",	{	0x48,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "lslb",	{	0x58,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "lsld",	{	0x1048,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "lsr",	{	0x04,	0x64,	0x74,	-0x1	},	insn_gen0 },
	{ "lsra",	{	0x44,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "lsrb",	{	0x54,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "lsrd",	{	0x1044,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "lsrw",	{	0x1054,	-0x1,	-0x1,	-0x1	},	insn_inh },

	{ "mul",	{	0x3d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "muld",	{	0x118f,	0x119f,	0x11af,	0x11bf	},	insn_gen16 },
	
	{ "neg",	{	0x00,	0x60,	0x70,	-0x1	},	insn_gen0 },
	{ "nega",	{	0x40,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "negb",	{	0x50,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "negd",	{	0x1040,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "nop",	{	0x12,	-0x1,	-0x1,	-0x1	},	insn_inh },
	
	{ "oim",	{	0x01,	0x61,	0x71,	-0x1	},	insn_logicmem },
	{ "ora",	{	0x9a,	0xaa,	0xba,	0x8a	},	insn_gen8 },
	{ "orb",	{	0xda,	0xea,	0xfa,	0xca	},	insn_gen8 },
	{ "orcc",	{	0x1a,	-0x1,	-0x1,	0x1a	},	insn_imm8 },
	{ "ord",	{	0x109a,	0x10aa,	0x10ba,	0x108a	},	insn_gen16 },
	{ "orr",	{	0x1035,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	
	{ "pshs",	{	0x34,	-0x1,	-0x1,	-0x1	},	insn_rlist },
	{ "pshsw",	{	0x1038,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "pshu",	{	0x36,	-0x1,	-0x1,	-0x1	},	insn_rlist },
	{ "pshuw",	{	0x103a,	-0x1,	-0x1,	-0x1	},	insn_inh	},
	{ "puls",	{	0x35,	-0x1,	-0x1,	-0x1	},	insn_rlist },
	{ "pulsw",	{	0x1039,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "pulu",	{	0x37,	-0x1,	-0x1,	-0x1	},	insn_rlist },
	{ "puluw",	{	0x103b,	-0x1,	-0x1,	-0x1	},	insn_inh },
	
	{ "rol",	{	0x09,	0x69,	0x79,	-0x1	},	insn_gen0 },
	{ "rola",	{	0x49,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rolb",	{	0x59,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rold",	{	0x1049,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rolw",	{	0x1059,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "ror",	{	0x06,	0x66,	0x76,	-0x1	},	insn_gen0 },
	{ "rora",	{	0x46,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rorb",	{	0x56,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rord",	{	0x1046,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rorw",	{	0x1056,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rti",	{	0x3b,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "rts",	{	0x39,	-0x1,	-0x1,	-0x1	},	insn_inh },
	
	{ "sbca",	{	0x92,	0xa2,	0xb2,	0x82	},	insn_gen8 },
	{ "sbcb",	{	0xd2,	0xe2,	0xf2,	0xc2	},	insn_gen8 },
	{ "sbcd",	{	0x1092,	0x10a2,	0x10b2,	0x1082	},	insn_gen16 },
	{ "sbcr",	{	0x1033,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "sex",	{	0x1d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "sexw",	{	0x14,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "sta",	{	0x97,	0xa7,	0xb7,	-0x1	},	insn_gen0 },
	{ "stb",	{	0xd7,	0xe7,	0xf7,	-0x1	},	insn_gen0 },
	{ "stbt",	{	0x1137,	-0x1,	-0x1,	-0x1	},	insn_bitbit },
	{ "std",	{	0xdd,	0xed,	0xfd,	-0x1	},	insn_gen0 },
	{ "ste",	{	0x1197,	0x11a7,	0x11b7,	-0x1	},	insn_gen0 },
	{ "stf",	{	0x11d7,	0x11e7,	0x11f7,	-0x1	},	insn_gen0 },
	{ "stq",	{	0x10dd,	0x10ed,	0x10fd,	-0x1	},	insn_gen0 },
	{ "sts",	{	0x10df,	0x10ef,	0x10ff,	-0x1	},	insn_gen0 },
	{ "stu",	{	0xdf,	0xef,	0xff,	-0x1	},	insn_gen0 },
	{ "stw",	{	0x1097,	0x10a7,	0x10b7,	-0x1	},	insn_gen0 },
	{ "stx",	{	0x9f,	0xaf,	0xbf,	-0x1	},	insn_gen0 },
	{ "sty",	{	0x109f,	0x10af,	0x10bf,	-0x1	},	insn_gen0 },
	{ "suba",	{	0x90,	0xa0,	0xb0,	0x80	},	insn_gen8 },
	{ "subb",	{	0xd0,	0xe0,	0xf0,	0xc0	},	insn_gen8 },
	{ "subd",	{	0x93,	0xa3,	0xb3,	0x83	},	insn_gen16 },
	{ "sube",	{	0x1190,	0x11a0,	0x11b0,	0x1180	},	insn_gen8 },
	{ "subf",	{	0x11d0,	0x11e0,	0x11f0,	0x11c0	},	insn_gen8 },
	{ "subr",	{	0x1032,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "subw",	{	0x1090,	0x10a0,	0x1090,	0x1080	},	insn_gen8 },
	{ "swi",	{	0x3f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "swi2",	{	0x103f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "swi3",	{	0x113f,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "sync",	{	0x13,	-0x1,	-0x1,	-0x1	},	insn_inh },
	
	// note: 		r+,r+	r-,r-	r+,r	r,r+
	{ "tfm",	{	0x1138,	0x1139,	0x113a,	0x113b	},	insn_tfm },

	{ "tfr",	{	0x1f,	-0x1,	-0x1,	-0x1	},	insn_rtor },
	{ "tim",	{	0x0b,	0x6b,	0x7b,	-0x1	},	insn_logicmem },
	{ "tst",	{	0x0d,	0x6d,	0x7d,	-0x1	},	insn_gen0 },
	{ "tsta",	{	0x4d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "tstb",	{	0x5d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "tstd",	{	0x104d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "tste",	{	0x114d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "tstf",	{	0x115d,	-0x1,	-0x1,	-0x1	},	insn_inh },
	{ "tstw",	{	0x105d,	-0x1,	-0x1,	-0x1	},	insn_inh },

	{ "org",	{ -1, -1, -1, -1 },	pseudo_org },

	{ "equ",	{ -1, -1, -1, -1 },	pseudo_equ,	0,	0,	1 },
	{ "=",		{ -1, -1, -1, -1 },	pseudo_equ,	0,	0,	1 },
	{ "extern",	{ -1, -1, -1, -1 },	pseudo_extern,	0,	0,	1 },
	{ "external",	{ -1, -1, -1, -1 },	pseudo_extern,	0,	0,	1 },
	{ "import",	{ -1, -1, -1, -1 },	pseudo_extern,	0,	0,	1 },
	{ "export",	{ -1, -1, -1, -1 },	pseudo_export,	0,	0,	1 },


	{ "rmb", 	{ -1, -1, -1, -1 }, pseudo_rmb },
	{ "rmd", 	{ -1, -1, -1, -1 }, pseudo_rmd },
	{ "rmq", 	{ -1, -1, -1, -1 }, pseudo_rmq },

	{ "zmb", 	{ -1, -1, -1, -1 }, pseudo_zmb },
	{ "zmd", 	{ -1, -1, -1, -1 }, pseudo_zmd },
	{ "zmq", 	{ -1, -1, -1, -1 }, pseudo_zmq },

	{ "fcc",	{ -1, -1, -1, -1 },	pseudo_fcc },
	{ "fcn",	{ -1, -1, -1, -1 },	pseudo_fcn },
	{ "fcs",	{ -1, -1, -1, -1 },	pseudo_fcs },

	{ "fcb",	{ -1, -1, -1, -1 },	pseudo_fcb },
	{ "fdb",	{ -1, -1, -1, -1 },	pseudo_fdb },
	{ "fqb",	{ -1, -1, -1, -1 },	pseudo_fqb },

	{ "end", 	{ -1, -1, -1, -1 }, pseudo_end },

	{ "include", { -1, -1, -1, -1 }, pseudo_include },
	
	{ "align", { -1, -1, -1, -1 },	pseudo_align },

	{ "error",	{ -1, -1, -1, -1},	pseudo_error },

	{ "ifeq",	{ -1, -1, -1, -1}, 	pseudo_ifeq, 1 },
	{ "ifne",	{ -1, -1, -1, -1}, 	pseudo_ifne, 1 },
	{ "if",		{ -1, -1, -1, -1}, 	pseudo_ifne, 1 },
	{ "ifgt",	{ -1, -1, -1, -1}, 	pseudo_ifgt, 1 },
	{ "ifge",	{ -1, -1, -1, -1}, 	pseudo_ifge, 1 },
	{ "iflt",	{ -1, -1, -1, -1}, 	pseudo_iflt, 1 },
	{ "ifle",	{ -1, -1, -1, -1}, 	pseudo_ifle, 1 },
	{ "endc",	{ -1, -1, -1, -1}, 	pseudo_endc, 1 },
	{ "else",	{ -1, -1, -1, -1}, 	pseudo_else, 1 },
	{ "ifdef",	{ -1, -1, -1, -1},	pseudo_ifdef, 1},
	{ "ifndef",	{ -1, -1, -1, -1},	pseudo_ifndef, 1},

	{ "macro",	{ -1, -1, -1, -1}, 	pseudo_macro,	1,	0,	1 },
	{ "endm",	{ -1, -1, -1, -1},	pseudo_endm,	1,	1,	1 },

	{ "setdp", 	{ -1, -1, -1, -1},	pseudo_setdp },
	{ "set",	{ -1, -1, -1, -1},	pseudo_set,	0,	0,	1 },

	{ "section",	{ -1, -1, -1, -1},	pseudo_section },
	{ "sect",	{ -1, -1, -1, -1},	pseudo_section },
	{ "ends",	{ -1, -1, -1, -1},	pseudo_endsection },
	{ "endsect",	{ -1, -1, -1, -1},	pseudo_endsection },
	{ "endsection",	{ -1, -1, -1, -1},	pseudo_endsection },
	
	{ "pragma",	{ -1, -1, -1, -1},	pseudo_pragma },
	{ "*pragma",	{ -1, -1, -1, -1},	pseudo_starpragma },
	

	/* flag end of table */	
	{ NULL,		{ -0x1, -0x1, -0x1, -0x1 }, insn_inh }
};